Clock-independent mode register setting methods and apparatuses

ABSTRACT

Mode register setting methods and apparatuses for semiconductor devices are provided in order to suppress a limit in the frequency at which a mode register of a semiconductor device operates from occurring before the semiconductor device carries out a typical write or read operation, as the frequency at which the semiconductor device operates increases. The mode register setting methods and apparatuses may be applied, for example, to DDR-type semiconductor devices. If a chip selection signal /CS maintains a logic low level for at least a first amount of time, a semiconductor device may initiate a clock-independent mode register setting operation. In the clock-independent mode register setting operation, a mode register set (MRS) command and an MRS code bit may be sampled when the logic level of a data strobe signal applied to the semiconductor device transitions from a logic low level to a logic high level. Therefore, it is possible to solve the problem of restrictions regarding the operating frequency of the mode register of the semiconductor device by performing a test mode register setting operation independent of a clock signal applied to the semiconductor device.

PRIORITY STATEMENT

This application claims priority under 35 U.S.C. §119 to Korean PatentApplication No. 10-2005-0060791, filed on Jul. 6, 2005, in the KoreanIntellectual Property Office (KIPO), the entire contents of which isincorporated herein by reference.

BACKGROUND

1. Field of the Invention

Example embodiments of the present invention relate to semiconductormemory devices, for example, apparatuses for setting and/or selecting amode register set in response to an input address and methods for thesame.

2. Description of the Conventional Art

Synchronous memory devices (e.g., DDR SDRAMs, etc.) may include aconventional mode register for setting various parameters correspondingto product specifications and/or a test mode register for improvingproduct efficiency when analyzing memory devices. In this way, moderegister setting operations may be carried out in response to a clocksignal.

FIG. 1 is a block diagram of a conventional mode register settingapparatus for performing a test mode register setting operation. Thetest mode setting operation may be performed in response to a clocksignal.

A mode register set (MRS) command may be applied to a synchronoussemiconductor memory device together with an address set. The MRS may beused for determining various factors related to an operating mode of asynchronous semiconductor memory device, for example, CAS latency and/orburst length. When an MRS command is applied to the synchronoussemiconductor memory device together with an address set (e.g., A7=‘1’),the synchronous semiconductor memory device may enter a test mode.

A test mode may be an operating mode for efficiently testing asemiconductor memory device when it is manufactured. A user may setparameters related to the operating mode of the semiconductor memorydevice, for example, CAS latency and/or burst length. The test mode maybe set in response to an address applied with an MRS command duringmanufacture of the semiconductor memory device.

Referring to FIG. 1, the conventional mode register setting apparatusmay include a command decoder 11, an address set decoder 12, and/or a Dflip-flop 13.

The command decoder 11 may output an MRS command MRS CMD in response toa plurality of input signals. The plurality of input signals may includea chip selection signal /CS, a row address strobe signal /RAS, a columnaddress signal /CAS, and/or a write enable signal /WE. The commanddecoder 11 may output an MRS command MRS CMD with a logic high level insynchronization with a clock signal CLK when the chip selection signal/CS, the row address strobe signal /RAS, the column address signal /CAS,and/or the write enable signal /WE become logic low level.

The address set decoder 12 may output an address set signal MRS CODE inresponse to a plurality of memory address signals A0 through An-1. Theaddress set signal MRS CODE may be enabled when the plurality of memoryaddress signals A0 through An-1 match a given, desired, or designatedaddress set.

The D flip-flop 13 may receive the MRS command MRS CMD output by thecommand decoder 11 through a clock input port and may receive theaddress set signal MRS CODE through a D input port. The D flip-flop 13may be set in response to the address set signal MRS CODE and the MRScommand MRS CMD, and may output a test mode activation signal TM. Thetest mode activation signal TM may enable a test mode.

The conventional mode register setting apparatus of FIG. 2 operates insynchronization with the clock signal CLK which may restrict thefrequency of a test MRS as the frequency of the semiconductor memorydevice increases.

FIG. 2 is an example timing diagram illustrating a tCK Schmoo analysisduring a clock period T1. The clock period T1 may correspond to a moderegister setting period and/or a normal mode operating period. A testMRS command may be applied during a mode register setting period. In oneexample, if a tCK limit is detected before test MRS command application,a desired test mode may not be set as desired. This may limit theanalysis of tCK margin variations in a normal mode. Accordingly, the tCKSchmoo analysis may not be performed as desired.

FIG. 3 is an example timing diagram illustrating a tCK Schmoo analysisduring a clock period T2. The clock period T2 may correspond to a moderegister setting period. A clock period T1 may correspond to a normalmode operating period. The detection of a tCK limit at the beginning ofa mode register setting period may be suppressed due to the clock periodbeing T2. Thus, the tCK Schmoo analysis may be carried out in a normalmode operating period. However, the example shown in FIG. 2 may resultin varying clock periods and/or frequency variations (e.g. DLL locking).

SUMMARY

Example embodiments of the present invention provide mode registersetting apparatuses, and methods for the same, which may be lessrestricted by operating frequencies of mode registers in synchronoussemiconductor memory devices.

Example embodiments of the present invention provide mode registersetting apparatuses, and methods for the same, in which mode registersof semiconductor memory devices may set more freely, regardless of thefrequency of a clock signal.

In at least one example embodiment of the present invention, whether alogic level of a first control signal input to a first input pin of thesemiconductor device transitions from a second logic level to a firstlogic level may be determined. The logic level of a second controlsignal input to a second input pin of the semiconductor device may betransitioned while the first control signal maintains the first logiclevel for a first amount of time. The MRS may be set using a moderegister setting command signal and/or an address signal when the logiclevel of the second control signal transitions to a second logic level.The second control signal may maintain the second logic level for atleast one cycle of the clock signal.

In example embodiments of the present invention, the second controlsignal may maintain the changed logic level for one cycle of a clocksignal. The second control signal may maintain the changed logic levelfor any number of cycles of a clock signal. The amount of time at whichthe first control signal may maintain a logic level may be determined bya plurality of flip-flops connected in series. The plurality offlip-flops may be synchronized with the clock signal, and may transmitthe first control signal through the plurality of flip-flops.

In example embodiments of the present invention, an MRS initiationdetection signals may be generated if the first control signal maintainsthe first level for a given amount of time. The setting may includesetting the MRS in response to MRS initiation detection signals, forexample, when the logic level of the second control signal transitions.

Another example embodiment of the present invention provides a moderegister setting apparatus for setting a mode register set (MRS) of asemiconductor device. The mode register setting apparatus may include aMRS initiation determination circuit. The MRS initiation determinationcircuit may generate, during any stage of initializing the semiconductordevice, a MRS initiation detection signal when a first control signaltransitions to a first logic level and maintains the first logic levelfor a given amount of time. The mode register setting apparatus mayfurther include a mode register setting control circuit. The moderegister setting control circuit may output a mode register settingcontrol signal in response to the MRS initiation detection signal and asecond control signal transitioning to a second logic level. The secondcontrol signal may maintain the second logic level for at least onecycle of a clock signal.

In example embodiments of the present invention, the second controlsignal may maintain the second logic level for one or a plurality ofclock cycles.

According to example embodiments of the present invention, a moderegister setting apparatus may further include a mode register settingcircuit, which may set the MRS in response to the mode register settingcontrol signal using mode register setting command signals and/or anaddress signal. The MRS initiation determination circuit may determinean amount of time to maintain a logic level by transmitting the controlsignal through a plurality of flip-flops. The plurality of flip-flopsmay be connected in series and may operate in synchronization with theclock signal.

At least one other example embodiment of the present invention providesa mode register setting apparatus for setting a mode register set (MRS)of a semiconductor device. The mode register setting apparatus mayinclude a mode register setting control circuit. The mode registersetting control circuit may output a mode register setting controlsignal in response to a detection signal, a clock signal, and/or a firstcontrol signal transitioning to a first logic level. The first controlsignal may be independent of the clock signal. The mode register settingapparatus may include a mode register setting circuit for setting themode register set in response to the mode register setting controlsignal using a mode register setting command signal and/or an addresssignal.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are intended to depict example embodiments ofthe present invention and should not be interpreted to limit the scopethereof. The accompanying drawings are not to be considered as drawn toscale unless explicitly noted. The present invention will become moreapparent by describing in detail example embodiments thereof withreference to the attached drawings in which:

FIG. 1 is an example block diagram of a conventional mode registersetting apparatus;

FIG. 2 is an example timing diagram illustrating a clock period reducedto Ti for both a mode register setting period and a write/read operationperiod for a tCK Schmoo analysis;

FIG. 3 is an example timing diagram illustrating a clock period fixed atT2 for a mode register setting period and reduced to T1 for a normalmode operating period for a tCK Schmoo analysis;

FIG. 4 is a block diagram of a clock-independent mode register settingapparatus, according to an example embodiment of the present invention;

FIG. 5 is a timing diagram illustrating a clock-independent moderegister setting method performed by a clock-independent mode registersetting apparatus, according to an example embodiment of the presentinvention;

FIG. 6 illustrates a circuit for determining when to initiate and/orterminate a clock-independent MRS operation, according to an exampleembodiment of the present invention; and

FIG. 7 is illustrates a clock-independent mode register setting controlcircuit and a mode register setting circuit, according to an exampleembodiment of the present invention.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS OF THE PRESENT INVENTION

Example embodiments of the present invention are described more fullyhereinafter with reference to the accompanying drawings, in whichexample embodiments of the invention are shown. This invention may,however, be embodied in many different forms and should not be construedas limited to the example embodiments of the present invention set forthherein. Rather, these example embodiments of the present invention areprovided so that this disclosure will be thorough and complete, and willfully convey the scope of the invention to those skilled in the art. Inthe drawings, the size and relative sizes of layers and regions may beexaggerated for clarity.

It will be understood that when an element or layer is referred to asbeing “on,” “connected to” or “coupled to” another element or layer, itcan be directly on, connected or coupled to the other element or layeror intervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on,” “directly connected to”or “directly coupled to” another element or layer, there are nointervening elements or layers present. Like numbers refer to likeelements throughout the figures and specification. As used herein, theterm “and/or” includes any and all combinations of one or more of theassociated listed items.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, components, regions, layersand/or sections, these elements, components, regions, layers and/orsections should not be limited by these terms. These terms are only usedto distinguish one element, component, region, layer or section fromanother element, component, region, layer or section. Thus, a firstelement, component, region, layer or section discussed below could betermed a second element, component, region, layer or section withoutdeparting from the teachings of the present invention.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a,” “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “includes”and/or “including”, when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,components, and/or groups thereof but do not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

Example embodiments of the present invention will now be described morefully with reference to the accompanying drawings. In the drawings, likereference numerals represent like elements.

FIG. 4 is a block diagram of a clock-independent mode register settingapparatus, according to an example embodiment of the present invention.As shown, the clock-independent mode register setting apparatus 40 mayinclude a mode register setting initiation determination circuit 41, amode register setting control circuit 42, an address set decoder 43, acommand decoder 44, and/or a mode register setting circuit 45.

Referring to FIG. 4, the mode register setting initiation determinationcircuit 41 may receive a clock signal CLK and a chip selection signal/CS. If the chip selection signal /CS maintains a logic low level for agiven or designated amount of time after transitioning to the logic lowlevel, the mode register setting initiation determination circuit 41 mayoutput a mode register setting initiation detection signal MRS_ST to themode register setting control circuit 42. The mode register settinginitiation detection signal MRS_ST may enable a clock-independent MRSoperation.

To determine whether the chip selection signal maintains a logic lowlevel for a given amount of time, the mode register setting initiationdetermination circuit 41 may sample the chip select signal /CS when thelogic level of the clock signal CLK transitions from a logic high levelto a logic low level.

The mode register setting control circuit 42 may output a mode registersetting control signal MRS_CT in response to the mode register settinginitiation detection signal MRS_ST and a transition of the logic levelof a data strobe signal DQS input to the semiconductor memory devicefrom a logic low level to a logic high level.

The address set decoder 43 may output an MRS code signal MRS CODE inresponse to a plurality of memory address signals A0 through An-1. Theplurality of memory address signals A0 through An-1 may be applied froman external source. The MRS code signal MRS CODE may be enabled when theplurality of memory address signals A0 through An-1 match a given set ofaddresses. The MRS code signal MRS CODE may indicate whether a currentmode is a test mode or a normal operation mode.

The command decoder 44 may output the MRS command MRS CMD in response toat least one of a plurality of input signals. The plurality of inputsignals may include the chip selection signal /CS, a row address strobesignal /RAS, a column address signal /CAS, a write enable signal /WE,and/or any other suitable signal. Although example embodiments of thepresent invention have been described with regard to the chip selectsignal being input to the mode register setting initiation determinationcircuit 41, it will be understood that the row address strobe signal/RAS, column address signal /CAS, write enable signal /WE, and/or anyother suitable signal may be used.

The mode register setting circuit 45 may perform a mode register settingoperation in response to the mode register setting control signalMRS_CT, the MRS code MRS CODE output by the address set decoder 43,and/or the MRS command MRS CMD output by the command decoder 44.

According to at least one example embodiment of the present invention,the mode register setting apparatus 40 may initiate an MRS mode insynchronization with the data strobe signal DQS and independent of theclock signal CLK. The data strobe signal DQS may have a period greaterthan or equal to that of the clock signal CLK, and as a result, evenwhen the period of the clock signal CLK is reduced, the likelihood of atCK limit occurring too early may be suppressed.

A clock-independent mode register setting apparatus, according to anexample embodiment of the present invention, has been described asinitiating a mode register operation in synchronization with the datastrobe signal DQS. However, the clock-independent mode register settingapparatus may initiate a mode register setting operation insynchronization with any other suitable signal having a period greaterthan or equal to the clock signal CLK.

The time interval during which the data strobe signal DQS is at a logichigh level may be set by an external controller (not shown) such thatthe clock-independent mode register setting apparatus may initiate anMRS mode more stably.

FIG. 5 is an example timing diagram illustrating a clock-independentmode register setting method, according to an example embodiment of thepresent invention. As shown, the mode register setting initiationdetermination circuit 41 may sample a chip selection signal /CS when thelogic level of a clock signal CK transitions from a logic high level toa logic low level (51). If the sampled chip selection signal /CS isdetermined to have maintained a logic low level for a given amount oftime (52), the clock-independent mode register setting apparatus 40 mayinitiate an MRS mode (53). In an MRS mode setting period (56), anexternal controller (not shown) may generate an MRS command MRS CMDsetting an MRS of a semiconductor memory device, and may transmit a testmode code (e.g., an MRS code). The test mode code may indicate a testmode with or without an address signal ADDR.

The mode register setting control circuit 42 may transmit a moderegister setting control signal MRS_CT, for example, when a data strobesignal DQS transitions to a logic high level (55). The mode registersetting circuit 45 may receive the MRS command MRS CMD and the MRS codeMRS CODE and may set a test mode (54) in synchronization with the datastrobe signal DQS. The data strobe signal DQS may have a period greaterthan or equal to that of the clock signal CLK.

The clock-independent MRS mode may be terminated, for example, when thelogic level of the chip selection signal /CS transitions from a logiclow level to a logic high level (57).

FIG. 6 illustrates a mode register setting initiation determinationcircuit, according to an example embodiment of the present invention.The mode register setting initiation determination circuit 41 mayinclude a plurality of flip-flops 41_1 through 41 _(—) n which may beconnected in series. An input/output (I/O) node of each of the pluralityof flip-flops 41_1 through 41 _(—) n may be set at a first logic level(e.g., a logic high level). Each of the plurality of flip-flops 41_1through 41 _(—) n may be driven by the logic level of a clock signal CLKtransitioning from a logic high level (H) to a logic low level (L).

In example operation, flip-flop 41_1 may transmit a chip selectionsignal /CS to flip-flop 41_2 when the logic level of the clock signalCLK transitions from a logic high level to a logic low level, flip-flop41_2 may transmit the output of the flip-flop 41_1 to the flip-flop 41_3when the logic level of the clock signal CLK transitions from a logichigh level to a logic low level, and so on, until flip-flop 41 _(—) noutputs an output of the flip-flop 41 _(—) n-1 as a mode registersetting initiation detection signal MRS_ST.

According to at least some example embodiments of the present invention,the duration for which the chip selection signal maintains a logic lowlevel after the logic level of the clock signal CLK transitions from alogic high level to a logic low level may be determined by the number nof the plurality of flip-flops 41_1 through 41 _(—) n and/or a clocksignal CLK. As a result, a clock-independent MRS mode may be initiatedmore stably even as the frequency of the clock signal CLK increases. Ifthe chip selection signal /CS maintains a logic low level for n×2 cyclesof the clock signal CLK, the mode register setting initiation detectionsignal MRS_ST output by the flip-flop 41 _(—) n may transition to alogic low level.

In a normal mode operation, the chip selection signal /CS may transitionto a logic high level as the logic level of the clock signal CLKtransitions from a logic high level to a logic low level. In thisexample, the mode register setting initiation detection signal MRS_STmay maintain a logic high level.

FIG. 7 illustrates a mode register setting control circuit and a moderegister setting circuit, according to an example embodiment of thepresent invention. As shown, in a mode register setting control circuit42, a NAND gate 71 may receive a clock signal CLK and a mode registersetting initiation detection signal MRS_ST. An inverter 73 may invertthe mode register setting initiation detection signal MRS_ST, and a NANDgate 74 may perform a NAND operation on a data strobe signal DQS and anoutput of the inverter 73. An inverter 75 may invert an output of theNAND gate 74, and an OR gate 76 may perform an OR operation on an outputof the inverter 72 and an output of the inverter 75. The output of theOR gate 76 may be a mode register setting control signal MRS_CT.

Still referring to FIG. 7, in the mode register setting circuit 45, aflip-flop 77 may transmit an MRS command MRS CMD to an MRS logic circuit(not shown) when the mode register setting control signal MRS_CTtransitions to a logic high level. Flip-flop 78 may transmit an MRS codeto the MRS logic circuit when the mode register setting control signalMRS_CT transitions to a logic high level.

In one example, when the mode register initiation detection signalMRS_ST is at a logic high level, the NAND gate 71 may be an inverter,and the output of the inverter 72 may be the clock signal CLK. Theoutput of the inverter 73 may transition to a logic low level, and theoutput of the NAND gate 74 may transition to a logic high levelregardless of the logic level of the data strobe signal DQS. In thisexample, the output of the inverter 75 may transition to a logic lowlevel. As a result, the output of the OR gate 76 may become the outputof the inverter 72. According to at least some example embodiments ofthe present invention, when the mode register setting initiationdetection signal MRS_ST is at a logic high level, the output of the ORgate 76 (e.g., the mode register setting control signal MRS_CT) may bethe same as the clock signal CLK, and the mode register setting circuit45 may perform a mode register setting operation in synchronization withthe clock signal CLK.

In another example where the mode register setting initiation detectionsignal MRS_ST is at a logic low level, the output of the NAND gate 71may be at a logic high level, and the output of the inverter 72 may beat a logic low level. The output of the inverter 73 may be at a logichigh level, and the output of the inverter 75 may be the same as thedata strobe signal DQS. As a result, the output of the OR gate 76 may bethe same as the output of the inverter 75. In this example, when themode register setting initiation detection signal MRS_ST is at a logiclow level, the output of the OR gate 76 may be the same as the datastrobe signal DQS, and the mode register setting control signal MRS_CTmay transition to a logic low level when the data strobe signal DQStransitions to a logic low level.

Flip-flops 77 and 78 may sample the MRS command and the MRS code whenthe data strobe signal DQS transitions to a logic low level bytransmitting the MRS command and the MRS code to the MRS logic circuitwhen the logic level of the mode register setting control signal MRS_CTtransitions from a logic high level to a logic low level. In thisexample, a mode register setting operation may be performed regardlessof the clock signal CLK, and the MRS command and the MRS code may beapplied to the MRS logic circuit in synchronization with the data strobesignal DQS. The data strobe signal DQS may have a period greater than orequal to the clock signal CLK regardless of the frequency of the clocksignal CLK.

According to example embodiments of the present invention, mode registersetting operations may be terminated by applying a chip selection signal/CS with a logic high level as the logic level of an arbitrary clocksignal CLK, applied after the generation of the MRS command MRS CMD,transitions from a logic high level to a logic low level. The durationfor which the chip selection signal /CS maintains a logic high level maybe determined by multiplying the number n of the plurality of flip-flops41_1 through 41 _(—) n (e.g., n multiplied by the period of the clocksignal CLK).

Although discussed above with regard to the NAND gate 71, the inverter72, the NAND gate 74, and/or the inverter 75, these logic gates may bereplaced with any suitable combination of logic gates, for example, withAND gates.

Clock-independent mode register setting apparatuses, and methods for thesame, according to example embodiments of the present invention, may beless affected by frequency restrictions associated with a mode registersetting operation, and as a result, example embodiments of the presentinvention may suppress a tCK limit from occurring too early in a moderegister setting period, for example, even when the operating frequencyof a synchronous semiconductor memory device increases.

Example embodiments of the present invention provide more efficienthigher-frequency mode analysis, such as tCK Schmoo analysis, through theapplication of a plurality of MRS commands regardless of the frequencyat which a synchronous semiconductor memory device operates. Inaddition, causes of problems (e.g., faults, etc.) in a normal mode maybe diagnosed more easily by setting a test mode MRS independently of aclock signal.

Although example embodiments of the present invention have beendescribed, it will be obvious that the same may be varied in many ways.Such variations are not to be regarded as a departure from the spiritand scope of the present invention, and all such modifications areintended to be included within the scope of the present invention.

1. A clock-independent mode register setting method comprising:detecting a transition of a first control signal to a first logic level;transitioning a second control signal to a second logic level if thefirst control signal maintains the first logic level for a first timeperiod and a data strobe signal transitions to a third logic level; andsetting a mode register set using at least one of a mode registersetting command signal and an address signal based on the transitioningof the second control signal, and independent of a clock signal.
 2. Theclock-independent mode register setting method of claim 1, wherein thesecond control signal maintains the second logic level for at least oneclock cycle.
 3. The clock-independent mode register setting method ofclaim 1, wherein the second control signal maintains the second logiclevel for a plurality of clock cycles.
 4. The clock-independent moderegister setting method of claim 1, wherein the first control signal isa chip selection signal, and a duration for which the second controlsignal maintains the second logic level is determined by an externalcontroller.
 5. The clock-independent mode register setting method ofclaim 1, wherein the first time period is determined based on a numberof flip-flops connected in series, the flip-flops being synchronizedwith the clock signal.
 6. The clock-independent mode register settingmethod of claim 4, wherein the first control signal transitions to thefirst logic level in response to at least one transition of the clocksignal.
 7. The clock-independent mode register setting method of claim1, further including, transitioning a detection signal if the firstcontrol signal maintains the first level for at least the first timeperiod, wherein the mode register set is set in response to thetransitioning of the detection signal and the transition the data strobesignal.
 8. A clock-independent mode register setting apparatuscomprising: a determination circuit for detecting a transition of afirst control signal to a first logic level, and transitioning adetection signal if the first control signal maintains the first logiclevel for a first time period; and a mode register setting controlcircuit for outputting a mode register setting control signal inresponse to the transitioning of the detection signal and a transitionof a data strobe signal to a second logic level, the data strobe signalmaintaining the second logic level for at least one clock cycle.
 9. Theclock-independent mode register setting apparatus of claim 8, whereinthe data strobe signal maintains the second logic level for one clockcycle.
 10. The clock-independent mode register setting apparatus ofclaim 8, wherein the data strobe signal maintains the second logic levelfor a plurality of clock cycles.
 11. The clock-independent mode registersetting apparatus of claim 8, further including, a mode register settingcircuit for setting the mode register in response to the mode registerset control signal and based on a mode register setting command signaland an address signal.
 12. The clock-independent mode register settingapparatus of claim 11, wherein the first control signal is a chipselection signal, and a duration for which the mode register set controlsignal maintains the second logic level is based on the data strobesignal, the data strobe signal being set by an external controller. 13.The clock-independent mode register setting apparatus of claim 11,wherein the determination circuit determines the first time period basedon a number of flip-flops connected in series and operated insynchronization with a clock signal.
 14. The clock-independent moderegister setting apparatus of claim 13, wherein an output of a lastflip-flop in the plurality of flip-flops is the detection signal. 15.The clock-independent mode register setting apparatus of claim 11,wherein the control circuit further includes, a first AND gate forperforming an AND operation on the detection signal and the clocksignal, an inverter for inverting the detection signal and outputting aninverted signal, a second AND gate for performing an AND operation onthe inverted signal and the data strobe signal, and an OR gate forperforming an OR operation on an output of the first AND gate and anoutput of the second AND gate, and outputting a result of the ORoperation as the mode register setting control signal.
 16. Theclock-independent mode register setting apparatus of claim 15, whereinthe control circuit further includes, a first flip-flop for outputtingthe mode register setting command to the mode register setting circuitin response to the mode register set control signal, and a secondflip-flop for outputting an address set to the mode register settingcircuit in response to the mode register set control signal.
 17. Aclock-independent mode register setting apparatus for setting a moderegister set of a semiconductor device, the clock-independent moderegister setting apparatus comprising: a mode register setting controlcircuit for outputting a mode register set control signal in response toa detection signal, a clock signal, and a transition of a data strobesignal, at least the mode register set control signal being independentof the clock signal; and a mode register setting circuit for setting themode register set in response to the mode register set control signalusing a mode register setting command signal and an address signal. 18.The clock-independent mode register setting apparatus of claim 17,further including, a detection circuit for generating the detectionsignal based on a duration of time over which a first control signalmaintains a first logic level.
 19. The clock-independent mode registersetting apparatus of claim 17, wherein the a mode register settingcontrol circuit further includes, a first AND gate for performing an ANDoperation on the detection signal and the clock signal, an inverter forinverting the detection signal and outputting an inverted signal, asecond AND gate for performing an AND operation on the inverted signaland the detection signal, and an OR gate for performing an OR operationon an output of the first AND gate and an output of the second AND gate,and outputting a result of the OR operation as the mode register setcontrol signal.
 20. The clock-independent mode register settingapparatus of claim 17, wherein the mode register setting circuit furtherincludes, a first flip-flop for outputting the mode register settingcommand to the mode register setting circuit in response to the moderegister set control signal, and a second flip-flop for outputting anaddress set to the mode register setting circuit in response to the moderegister set control circuit.